Specializing RISC-V Cores for Performance and Power

Context

The internet-of-things is on the rise, creating a large volume of data that needs to be moved into a central server to be processed. An alternative is to process data as much as possible on the edge, instead of the server, reducing data transfers, and providing a faster response time for edge services. For example, machine learning inference from image data on the edge.

However, edge devices (like cameras, routers, drones, phones etc), are limited (in comparison to power servers) of power and compute power. This prevents the true rise of edge computing. One solution to better power/performance ratio is the use of more efficient hardware. Hardware is specialized for a task consumes less power, and is faster to execute.

Objectives

The RISC-V is a rising family of open-source processors designed for configurability and extension.

This work aims to: 1) add custom units to a RISC-V to achieve faster runtimes and lower power consumption, to 2) validate the design on FPGA, and (optionally, depending on time) 3) to reduce area usage by using runtime circuit reconfiguration (i.e., Dynamic Partial Reconfiguration on FPGA)

Proposed Work Plan

  • Familiarization with core concepts like Dynamic Partial Reconfiguration (DPR), the RISC-V, and existing tools an designs too be used as starting points (for example, the RISC-V Mini https://github.com/ucb-bar/riscv-mini, or the Gem5 processor simulator or alternatives)

  • Preparing a set of benchmarks to use for validation in the work

  • Preparing the first version of the state of the art

  • Generate a set of custom units for the RISC-V from graph analysis

  • Implement the units in a modern HDL design language such as Chisel3

  • Integrate the units into an open source Risc-V design

  • Evaluate the area and performance of the design versus the original, (with and without reconfiguration if time allows)

Details

References

FPGA RISC-V Binary Translation Compilers
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Last updated on Oct 20, 2021

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