Runtime Management of Heterogeneous Compute Resources in Embedded Systems

Motivation

In the embedded domain, it is not uncommon for compute platforms to be heterogeneous. That is, to contain a main processor, and several specialized co-processors for specific function. It is up to the programmer to understand the underlying hardware platform and schedule workload onto different components, and to synchronize their behavior.

One of the platforms used for this kind of approach are Field-Programmable-Gate-Arrays (FPGAs). Since manual hardware design is a difficult process, approaches like High-Level Synthesis automatically generate circuit descriptions from functions written in C/C++ code.

This major objective of this thesis is to design and implement a runtime software and/or hardware mechanism capable of determining which accelerators should be loaded onto the FPGA, and when they should be loaded. The autonomous decision making will use data such as: the values of the arguments of the functions that are being called, the order in which the functions are called, the execution time of the accelerators, the temporal overhead of switching accelerators via DPR, and others.

Proposed Work Plan

• Designing the base embedded system to apply the runtime resource management to. This will be done on the Xilinx ZCU102 Development Board. The hardcore ARM processor will host the application code, and the FPGA side will host the several accelerator slots;
• From a set of compute kernels, create the respective accelerator modules using High-Level Synthesis; multiple accelerators per function should be generated, each with different design parameters (e.g., throughput, size, reconfiguration time, etc);
• Develop, either in software, hardware, or a mixed design, a methodology for random forest selection which can determine when and which accelerators to load into which slots.

Details

• Status: Completed
• Student: Luís Miguel de Sousa
• Thesis Document
• GitHub Repository