An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis
Motivation
Reconfigurable fabrics, especially FPGAs, have become very sophisticated and complex computing platforms. Their customization features make them computing platforms of choice in many application domains.
Pathfinding algorithms calculate the shortest route between two vertices in a graph and have become increasingly important since they are essential for services such as traffic navigation. However, they can be computationally intensive, especially if we consider large maps.
The goal of this thesis is to implement a pathfinding algorithm used in traffic navigation on FPGA using High-Level Synthesis (i.e., C, OpenCL), and use source-to-source techniques to automatically explore the efficiency of several implementations according to certain criteria (e.g., execution time, occupied area).
This thesis will have the collaboration of IT4Innovations National Supercomputing Center of the Czech Republic which has extensive experience in traffic navigation services.
Proposed Work Plan
- Identification of the main methods and technologies to be used;
- Learning the technologies to be used (e.g., Xilinx tools);
- Development of a C/OpenCL implementation ;
- Development of strategies that enable the exploration of several versions of the implementation;
- Evaluation of the approach
- Dissertation writing
- Writing a scientific paper
Details
- Status: Completed
- Student: Pedro Filipe Silva
- Thesis Document