High Level Synthesis

An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis

The goal of this thesis is to implement a pathfinding algorithm used in traffic navigation on FPGA using High-Level Synthesis.

Nuno M.C. Paulino

Sep 1, 2021 Thesis

Runtime Management of Heterogeneous Compute Resources in Embedded Systems

This major objective of this thesis is to design and implement a runtime software and/or hardware mechanism capable of determining which accelerators should be loaded onto the FPGA, and when they should be loaded.

Nuno M.C. Paulino

Sep 1, 2021 Thesis