FPGA

This work is about compiling C code to systolic arrays via source-to-source.

This work is about abstracting CGRA architectures via a proposal for a common ISA.

This work is about customizing RISC-V processors with custom units.

This work is about using binary translation to create custom units for RISC-V processor pipelines.

The goal of this thesis is to implement a pathfinding algorithm used in traffic navigation on FPGA using High-Level Synthesis.

This major objective of this thesis is to design and implement a runtime software and/or hardware mechanism capable of determining which accelerators should be loaded onto the FPGA, and when they should be loaded.

The goal of this project is to devise and evaluate a complete FPGA-based, run-time reconfigurable infrastructure that supports the dynamic deployment of multiple K-NN accelerator cores.

Heuristics for runtime scheduling of workload onto accelerators in embedded systems.

SMILES is one of the main Research Lines of the Norte 2020 project Tec4Growth, involving all the 4 centres from the Computer Science cluster and 5 other centres from INESC TEC.

This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms.