Binary Translation

Compiling Trace Graphs to RISC-V Accelerators
This work is about re-compiling RISC-V instruction sequences to parallel compute engines.
Nuno M.C. Paulino
Oct 28, 2021 Thesis
Compiling for Spatial Computation Architectures
This work is about compiling C code to systolic arrays via source-to-source.
Nuno M.C. Paulino
Oct 20, 2021 Thesis
Specializing RISC-V Cores for Performance and Power
This work is about customizing RISC-V processors with custom units.
Nuno M.C. Paulino
Oct 20, 2021 Thesis
Generating Hardware Modules via Binary Translation of RISC-V Binaries
This work is about using binary translation to create custom units for RISC-V processor pipelines.
Nuno M.C. Paulino
Oct 18, 2021 Thesis