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Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
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Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
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