Publications

Nuno Paulino, Luís M. Pessoa (2023). Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver. IEEE Access.

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Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves (2022). Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation. 13th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2022, Porto, Portugal, July 20-22, 2022.

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Nuno Miguel Cardanha Paulino, Luís M. Pessoa, André Branquinho, Rafael Tavares, Igor Ferreira (2021). Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes. CoRR.

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Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira (2021). On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021.

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Hélder F. S. Campos, Nuno Paulino (2021). Multiple target tracking with interaction using an MCMC MRF Particle Filter. CoRR.

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Pedro Filipe Silva, João Bispo, Nuno Paulino (2021). FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example. International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021.

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Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves (2021). Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation. Joint European Conference on Networks and Communications & 6G Summit, EuCNC/6G Summit 2021, Porto, Portugal, June 8-11, 2021.

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Pedro Filipe Silva, João Bispo, Nuno Miguel Cardanha Paulino (2021). Building Beyond HLS: Graph Analysis and Others. CoRR.

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Hélder Campos, Nuno Paulino (2021). Augmentation of base classifier performance via HMMs on a handwritten character data set. CoRR.

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Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo (2021). A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR.

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Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso (2021). A Binary Translation Framework for Automated Hardware Generation. IEEE Micro.

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Nuno M.C. Paulino, João Canas Ferreira, João M. P. Cardoso (2020). Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. IEEE Access.

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Nuno Paulino, João Canas Ferreira, João M. P. Cardoso (2020). Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. ACM Comput. Surv..

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Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso (2020). Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020.

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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso (2019). Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst..

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Nuno Paulino, Luís Reis, João M. P. Cardoso (2017). On Coding Techniques for Targeting FPGAs via OpenCL. Parallel Computing is Everywhere, Proceedings of the International Conference on Parallel Computing, ParCo 2017, 12-15 September 2017, Bologna, Italy.

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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso (2017). Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst..

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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso (2015). Transparent acceleration of program execution using reconfigurable hardware. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015.

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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso (2015). A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst..

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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso (2014). Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2014, Milan, Italy, August 26-28, 2014.

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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira (2013). Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics.

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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira (2013). Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput..

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Nuno M.C. Paulino, João Canas Ferreira, João M. P. Cardoso (2013). Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings.

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João Bispo, Nuno M.C. Paulino, João M. P. Cardoso, João Canas Ferreira (2011). From Instruction Traces to Specialized Reconfigurable Arrays. 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011.

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