Publications

Human Activity Recognition with a Reconfigurable Intelligent Surface for Wi-Fi 6E
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Nuno Paulino, Mariana Oliveira, Francisco M. Ribeiro, Luís Outeiro, Luís M. Pessoa
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Vision-Radio Experimental Infrastructure Architecture Towards 6G
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Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa
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Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study
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Miguel Henriques, João Bispo, Nuno Paulino
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SpecRF-Posture: Exploring Specular Reflections for Human Posture Recognition
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Mariana Oliveira, Francisco M. Ribeiro, Nuno Paulino, Okan Yurduseven, Luís M. Pessoa
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CONVERGE: A Vision-Radio Research Infrastructure Towards 6G and Beyond
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Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa
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A DSL and MLIR Dialect for Streaming and Vectorisation
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Manuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino, João Bispo
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A Deep Learning Approach in RIS-based Indoor Localization
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Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa
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Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver
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Nuno Paulino, Luís M. Pessoa
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Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework
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Luís Miguel Sousa, João Bispo, Nuno Paulino
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Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning
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Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa
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Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper)
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João Bispo, Nuno Paulino, Luís Miguel Sousa
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A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver
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Nuno Paulino
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A Batch of Integer Data Sets for Clustering Algorithms
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Nuno Paulino
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Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation
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Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves
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Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes
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Nuno Miguel Cardanha Paulino, Luís M. Pessoa, André Branquinho, Rafael Tavares, Igor Ferreira
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On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
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Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira
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Multiple target tracking with interaction using an MCMC MRF Particle Filter
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Hélder F. S. Campos, Nuno Paulino
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Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
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Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
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FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
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Pedro Filipe Silva, João Bispo, Nuno Paulino
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Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation
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Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves
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Building Beyond HLS: Graph Analysis and Others
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Pedro Filipe Silva, João Bispo, Nuno Miguel Cardanha Paulino
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Augmentation of base classifier performance via HMMs on a handwritten character data set
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Hélder Campos, Nuno Paulino
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A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA
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Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo
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A Binary Translation Framework for Automated Hardware Generation
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Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso
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Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
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Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
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Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
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Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
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Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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On Coding Techniques for Targeting FPGAs via OpenCL
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Nuno Paulino, Luís Reis, João M. P. Cardoso
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Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration
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Nuno Miguel Cardanha Paulino
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Transparent acceleration of program execution using reconfigurable hardware
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso
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Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
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Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
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Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
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From Instruction Traces to Specialized Reconfigurable Arrays
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João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
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