REFLECT: Rendering FPGAs to Multi-Core Embedded Computing
This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms.
This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications (AOS) to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AOS specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow a seamless exploration of alternative architectures and run-time adaptive strategies allowing the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs.
Project Reference
Funded Under FP7-ICT
- https://cordis.europa.eu/project/id/248976
- Reference: 248976
Nuno M.C. Paulino
Professor Auxiliar Convidado, DEI
My research interests include tools and compiler for hardware, accelerator design, and edge and HPC computing.