Thesis

This work is about abstracting CGRA architectures via a proposal for a common ISA.

This work is about applying machine learning to performance modeling of applications on different targets.

This work is about customizing RISC-V processors with custom units.

This work is about using binary translation to create custom units for RISC-V processor pipelines.

The goal of this thesis is to implement a pathfinding algorithm used in traffic navigation on FPGA using High-Level Synthesis.

In this dissertation, the recently released version of the Bluetooth Low Energy protocol is explored, which introduces the ability to calculate the direction of signals, i.e, the Angle-of-Arrival.

This major objective of this thesis is to design and implement a runtime software and/or hardware mechanism capable of determining which accelerators should be loaded onto the FPGA, and when they should be loaded.

The objective of this work is to determine the method which allows for near-real-time tracking of the forklift, based on the Angle-of-Arrival of the Bluetooth beacons

The goal of this project is to devise and evaluate a complete FPGA-based, run-time reconfigurable infrastructure that supports the dynamic deployment of multiple K-NN accelerator cores.

Heuristics for runtime scheduling of workload onto accelerators in embedded systems.